1. Field of the Invention
The present invention relates to the field of inter-component communication in a computer system, in particular, the present invention is directed towards minimizing processor idle time during read and write cycles.
2. Description of the Related Art
Known computer systems are designed with multiple bus structures. A bus structure is a communication medium through which different components in a computer system transfer data signals. It is typical that a computer system will have a host bus and a system bus. Resources such as a Central Processing Unit (CPU), system Random Access Memory (RAM) or Read Only Memory (ROM) reside on a host bus. The host bus has a high operating speed which provides for high speed communication. A system bus is typically a slower speed bus to which peripheral resources are connected, e.g. keyboards, disk drives, displays etc.
It is necessary for operation of the computer system that the processor on the host bus write to or read from resources on the system bus. A buffer is positioned between the host bus and system bus to provide for inter-bus communications. One function of a buffer is to compensate for the differences in speed between the two bus structures. A second function of a buffer is the storing of resource access requests, i.e., read or write requests. Such a buffer that is used for storing writes is embodied in the 82353 EISA Bus Buffer, available from the Intel.RTM. Corporation of Santa Clara, Calif. Such a buffer is generally used in conjunction with other logic devices to perform the management of the requests.
With respect to this queuing of resource requests, it is common for a processor in a computer system to remain idle after a data "write" operation to a system resource, e.g. a hard disk, until the data is received by the resource. The sequence of writing data to a system resource is termed a "write cycle". A write cycle typically comprises the step of a processor issuing a write operation followed by an acknowledgement from the resource that the data has been received. The processor must remain idle until this acknowledgement is returned. The idle time increases in proportion to the activity on the system bus. This forced idle time results in a significant portion of potential processing time being unusable.
A known technique for minimizing the duration of a write cycle is to add intelligence, i.e. processing logic, to the buffer between a host bus and system bus. Typically, a First In First Out (FIFO) queuing means is incorporated into the intelligent buffer. An intelligent buffer, hereinafter referred to as a FIFO, will store a write command, send an acknowledgement back to the processor and initiate write cycles from the FIFO. The process of the FIFO accepting the data is termed "posting data". The acknowledgement is sent back to the processor so that it may continue processing. Write cycles are initiated on a First In First Out basis, when it is determined that the system bus is available to the FIFO.
As the FIFO is the bridge between the host bus and the system bus, the FIFO must also provide for "read" requests from the processor to system resources. Most system resources require that all outstanding "writes" to the resource be performed prior to any "reads". This requirement insures the integrity of the data being read. The process of performing all the writes is termed "flushing" the FIFO. In known FIFO systems, all the posted data in the FIFO is "flushed", rather than limiting the flush to the posted data that is associated with the resource from which data is to be "read". As the processor must remain idle until the requested data is provided (i.e. read), the potential for extensive idle time exists. It is desirable to flush only the posted data that is addressed to the system resource from which the "read" operation is to be performed.
One known technique for reducing the idle time caused by "read" operations is through data caching. Data caching reduces idle time by reducing the number of times a "read cycle" must go all the way to a system resource to access the data. Besides reducing idle time, data caching increases system performance by providing the processor access to a high speed dedicated resource. Here, frequently accessed data, e.g. a portion of the operating software or a database, is placed in the cache. If the caches are of the write through type, then write cycles will occur more frequently then read cycles on a system resource bus. Typically, system memory on the host bus is cached using a write through type cache. If the caches are of the write back type, then the number of write cycles on the system resources bus can be potentially reduced. However, write back cache operation across bus structures are difficult to implement. It is important to note that caches are only useful for resources that provide cache operation. Such resources that do not support cache operation require the traditional write cycle operation.
Although it is clear that a FIFO structure benefits "write cycles", any reduced idle time benefit gained is offset by "read cycles". Additionally, there are certain instances where a subsequent read or write may be able to use the contents of the FIFO. It is an overall object of the present invention to provide a FIFO system between bus structures that minimizes processor idle time and that exploits the contents of a FIFO in an advantageous manner.